{"id":187363,"title":"Senior FPGA Engineer (m/f/d)","company":"AES GmbH","city":"München","region":"Bayern","location":"München, Bayern","work_model":"unknown","employment_type":"full_time","employment":["full_time"],"roles":["embedded"],"visa":"not_mentioned","relocation":"not_mentioned","posted_at":"2026-09-10T00:00:00+00:00","tools":["FPGA"],"seniority":"senior","years_experience_min":null,"german_requirement":"not_mentioned","german_level":"unspecified","english_requirement":"required","english_level":"unspecified","team_language":"unknown","confidence":0.4,"method":"rules","language_badge":"Not stated","language_evidence":null,"requirements_snippet":null,"url":"https://careers.aes.gmbh/en/annonce/4591857-senior-fpga-engineer-mfd-80639-munchen","source":"careersite","agency":null,"description_text":"Acting as FPGA Work Package Lead for an engine or brake\ncontrol system development.\n\nSteer a team of engineers during the\ndevelopment phases of FPGA systems\n• Manage the teams technical\nwork scope\n• Define the work\npackages and coordinate the sequence of work execution\n• Support the\nproduct team with the development of the functional specification\n• Specify and align\nthe technical interfaces with our hardware and software teams\n• Monitor the work\nresults of your team and generate a progress reporting\n• Be the technical\nfocal point for your team and the project manager\n• Manage internal\nand external, national and international customers and suppliers\n\nBe an active part in the FPGA design and\nverification activities\n• Define and\ndocument new conceptual designs based on upper-level functional requirements\n• Write and/or\nvalidate the functional FPGA specifications\n• Develop,\nimplement and test your designs and show compliance to the requirements\n• Participate in\ntechnical reviews on design life cycle data\n• Define and\nvalidate test strategies and test objectives\n• Perform and/or\nreview verification elaboration and execution activities","responsibilities_text":null,"requirements_text":null,"status":"open","duplicate_of":null,"first_seen":"2026-11-05T07:53:47.648673+00:00","responsibilities_summary":null,"requirements_summary":null,"all_tools":["FPGA"],"posting_language":"en","evidence":[],"years_experience_max":null,"mobility_evidence":[],"model_version":"rules-8","english_badge":"English required","company_id":42257}